Astera Labs
Semiconductor Manufacturing
Is Astera Labs hiring?
Yes. As of November 4, 2026, Astera Labs has 178 open roles on Metaintro. 54 were posted in the last 30 days.
Open roles
Newest first. Pay shown when the posting lists it.
RoleLocationSetupPayPosted
- Technical Lead Digital Design EngineerScience, Technology, Engineering, and MathSan Jose, California, United States · $160K/yrSan Jose, California, United States—$160K/yr3d ago
- Senior Principal Sourcing Manager – Capital EquipmentOperations ManagementSan Jose, California, United States · $190K – $240K/yrSan Jose, California, United States—$190K – $240K/yr3d ago
- Principal AI Product ManagerProduct/Project ManagementSan Jose, California, United States · $185K – $240K/yrSan Jose, California, United States—$185K – $240K/yr3d ago
- Principal Digital Design EngineerScience, Technology, Engineering, and MathSan Jose, California, United States · $185K/yrSan Jose, California, United States—$185K/yr3d ago
- Staff / Principal ASIC Design EngineerScience, Technology, Engineering, and MathHaifa District, IsraelHaifa District, Israel——4d ago
- DFT EngineerScience, Technology, Engineering, and MathHaifa District, IsraelHaifa District, Israel——4d ago
- Staff Physical Design Engineer - SoC EMIR EngineerScience, Technology, Engineering, and MathHaifa District, IsraelHaifa District, Israel——4d ago
- Senior ASIC Design EngineerScience, Technology, Engineering, and MathHaifa District, IsraelHaifa District, Israel——4d ago
Hiring pattern
How fast Astera Labs is adding roles, and how they're set up.
New roles each monthRoles first posted in the month
39
39
51
54
15
JulyAugustSeptemberOctoberNovember
How roles are set upShare of open roles
3%
1%
19%
77%
HybridRemoteOn-siteNot stated
AI launches and partners
What Astera Labs has launched and who it works with on AI.
- LaunchLeo Smart Memory Controller FamilyAstera Labs bolsters its Leo Smart Memory Controller Family for Agentic AI and general-purpose cloud workloads.
- LaunchLeo Smart Memory ControllerThe expanded Leo Smart Memory Controller family provides fabric-attached memory for Agentic AI, with CXL 3.2 expansion, pooling, and sharing.
- LaunchScorpio X-Series Smart Fabric SwitchAstera Labs extends its leadership in open AI scale-up networking with a new 320 Lane Scorpio X-Series Smart Fabric Switch.
- LaunchAries PCIe Smart RetimerThe Aries PCIe Smart Retimer is purpose-built for AI server channels, delivering signal integrity and link stability over long distances for modular boards with multiple high-speed connectors.
Skills they ask for
Most frequent across open postings.
Most requested skills
- Python
- Signal integrity
- Timing closure
- PCIe
- SystemVerilog
- RTL design
- Ethernet
- SerDes
- UVM
- C/C++
- CXL
- Power integrity
Tech stack
- Security
- CookieYes
- CMS
- WordPress
- Analytics
- Google Tag Manager
- CDN
- Amazon CloudFront
- Libraries
- jQuery
- Tailwind CSS
Company facts
- Headquarters
- San Jose, US
- Employees
- 501–1,000
- Founded
- 2017
- Industry
- Semiconductor Manufacturing
- Sector (NAICS)
- Manufacturing
- Ticker
- ALAB
- Peer
- Applied Materials
- Website
- asteralabs.com
- Careers
- asteralabs.com/careers
Sources: Employees from Wikipedia (CC BY-SA 4.0) · Founded from Wikidata
Roles by location
Where Astera Labs is hiring. Pick a city to see its roles.
Similar companies
Companies in the same industry as Astera Labs that are hiring now.
Questions about Astera Labs
- Is Astera Labs hiring?
- Yes. As of November 4, 2026, Astera Labs has 178 open roles on Metaintro. 54 were posted in the last 30 days. The most are in Science, Technology, Engineering, and Math (130), Developer (12), and Operations Management (8).
- Where is Astera Labs hiring?
- Astera Labs is hiring in San Jose, Tel Aviv, Haifa District, Israel, Bengaluru, Taipei, and Toronto, with the most open roles in San Jose.
- Does Astera Labs offer remote or hybrid work?
- 3% of open roles are hybrid and 1% are remote.
- What skills does Astera Labs look for?
- Its open roles most often ask for Python, Signal integrity, Timing closure, PCIe, and SystemVerilog.